Senior RTL Design Engineer
About the Role
A frontier AI evaluation initiative is seeking experienced digital hardware engineers to support the assessment and improvement of advanced AI systems operating within semiconductor design and verification workflows. The project focuses on real-world silicon development environments, requiring deep technical expertise across modern ASIC design methodologies.
This opportunity is ideal for engineers with strong RTL design or verification backgrounds who are comfortable solving complex technical challenges, reviewing design tradeoffs, and working independently within highly technical project environments. Candidates may contribute through either digital design or design verification specializations.
The work involves analyzing chip development workflows, creating and evaluating engineering scenarios, reviewing technical outputs, and applying industry best practices across RTL development and verification processes. Success depends on strong digital design fundamentals, rigorous debugging skills, and clear technical communication.
What You'll Do
- Design and develop RTL components using Verilog and SystemVerilog
- Analyze and review digital architectures, datapaths, and control logic
- Debug RTL issues using simulation tools and waveform analysis
- Support synthesis, timing analysis, linting, CDC validation, and design quality checks
- Create and maintain technical documentation describing design decisions and tradeoffs
- Collaborate with architecture, implementation, and verification stakeholders
- Develop verification plans, testbenches, assertions, and coverage strategies where applicable
- Evaluate engineering workflows and contribute to AI system assessment initiatives
- Review simulation results, debug reports, and technical artifacts
- Apply industry-standard ASIC design and verification methodologies
Requirements
- 3–10 years of experience in RTL design, ASIC development, or design verification
- Strong proficiency in Verilog and/or SystemVerilog
- Solid understanding of FSMs, datapaths, pipelines, FIFOs, arbiters, clock domains, reset strategies, and bus protocols
- Experience with ASIC design flows including synthesis, timing analysis, linting, CDC, and related validation processes
- Experience using EDA tools for simulation, waveform debugging, synthesis, and verification activities
- Strong debugging and root-cause analysis skills
- Ability to produce clear technical documentation and communicate engineering tradeoffs
- Strong collaboration and cross-functional communication abilities
- Experience leveraging AI or LLM-based tools to improve engineering productivity and workflow efficiency
- Availability for high-volume project engagement with approximately 40 hours per week
- Authorized to work remotely from the United States or Canada
- Preferred qualifications:
- Experience with AMBA protocols including AXI, AHB, or APB
- Background in CPU, GPU, AI/ML accelerators, networking, memory subsystems, PCIe, high-speed I/O, SoC interconnects, or low-power design
- Experience with SystemVerilog Assertions (SVA), UVM, constrained-random verification, and coverage-driven methodologies
- Exposure to formal verification techniques
- Experience developing reusable verification IP, scoreboards, reference models, or regression infrastructure
- Familiarity with advanced semiconductor development environments and large-scale silicon programs