Senior RTL Design Engineer – AI Hardware Evaluation
About the Role
A leading AI hardware evaluation initiative is seeking experienced digital design and verification engineers to contribute expertise in advanced silicon development workflows. The project focuses on assessing and improving AI systems’ ability to support real-world chip design and verification tasks.
This opportunity is ideal for senior engineers with strong ASIC development backgrounds, including RTL design, digital architecture, verification methodologies, and hardware debugging. Candidates should be comfortable applying engineering judgment, reviewing technical workflows, and communicating complex design decisions clearly.
The work involves evaluating and supporting chip design scenarios across RTL development, verification, simulation, and hardware validation processes. Success requires strong knowledge of digital design fundamentals, industry-standard EDA workflows, and the ability to analyze technical tradeoffs in complex semiconductor environments.
What You'll Do
- Design and evaluate digital RTL modules using Verilog and SystemVerilog
- Develop and review hardware design workflows for ASIC development environments
- Analyze RTL implementations including FSMs, datapaths, pipelines, FIFOs, and arbitration logic
- Review clock, reset, and bus interface design approaches
- Evaluate ASIC design processes including lint, synthesis, timing analysis, CDC, and DFT considerations
- Debug RTL issues using simulation outputs, logs, and waveform analysis
- Develop and assess verification strategies using SystemVerilog and UVM methodologies
- Review verification environments, testbenches, assertions, and coverage approaches
- Analyze constrained-random testing, functional coverage, and regression workflows
- Create technical documentation, design reviews, and engineering assessments
- Evaluate the application of AI-assisted tools in chip design and verification workflows
- Collaborate across architecture, design, verification, and implementation functions
Requirements
- Located in the United States or Canada
- 3–10 years of professional experience in digital RTL design or semiconductor verification
- Strong proficiency in Verilog and SystemVerilog
- Strong understanding of digital design fundamentals including:
- Finite state machines (FSMs)
- Datapaths
- Pipelines
- FIFOs
- Arbiters
- Clock and reset domains
- Bus protocols
- Experience with ASIC design or verification workflows
- Familiarity with EDA tools for simulation, waveform debugging, linting, CDC analysis, synthesis, timing analysis, or coverage analysis
- Ability to write clear technical documentation and communicate engineering tradeoffs
- Strong debugging skills using simulation results and development tools
- Ability to work independently in a remote engineering environment
- Availability for full-time engagement and approximately 40 hours per week preferred
- Experience with AMBA protocols including AXI, AHB, or APB preferred
- Experience with CPU, GPU, ML accelerator, networking, memory subsystem, PCIe, high-speed I/O, SoC interconnect, or low-power design preferred
- Experience with formal verification or SystemVerilog/UVM verification environments preferred
- Experience developing reusable verification IP, scoreboards, reference models, or coverage-driven regression systems preferred
- Familiarity with LLM-based tools for RTL development, verification, debugging, test generation, documentation, or coverage analysis preferred
- Experience contributing to AI evaluation, hardware research, or engineering quality assessment projects preferred
- Ability to commit to multi-month project-based engineering work preferred